1. Field of the Invention
This invention relates to the field of excess energy protection schemes for semiconductor devices.
2. Background Art
Semiconductor devices, whether utilized as part of an integrated circuit or as a discrete component, are often subject to excess energy events. An excess energy event is a surge of power, often caused by a voltage or current spike, which can damage the semiconductor device itself, or lead to degradation or failure of metal contacts associated with the device. When a device is subjected to an excess energy event, the device dissipates the power as heat. Power is proportional to the square of the voltage and the voltage at which power is dissipated is dependent on the breakdown voltage of the affected device. By coupling to the protected device devices which have lower breakdown voltages, the power dissipated will be decreased, reducing the effect of heat in device failure. Additionally, by dissipating the excess energy through a protecting device, the active device is not exposed to voltage levels which can cause failure.
Certain types of excess energy events can adversely affect integrated circuits. A packaged integrated circuit can often build up large static charges as a result of handling, transportation, etc. The discharge of this static buildup in the integrated circuit is known as an electrostatic discharge (ESD) event. The voltages involved in such ESD events are very large, ranging as high as 250K volts. In addition, integrated circuits are subjected to other energy events from other sources, for example, voltage and current surges. These events create excess electrical energy which is dissipated within the circuit. Generally, the discharge path of this energy is from an input/output pad to ground and can involve the initial stages of the integrated circuit If the excess energy event exceeds the oxide breakdown voltage of a device in the initial stage, oxide breakdown and failure may result. Additionally, metal/silicon contacts and Pn junctions may be thermally damaged as a result of the heat dissipated from the excess energy event.
In order to limit the impact of excess energy events, protection devices are inserted between the pad and the initial stage of the integrated circuit One prior art protection device consists of a pair of diodes coupled to the input. One diode is coupled to a high power supply voltage level and the other is coupled to a low power supply voltage level or ground. A disadvantage of such a protection device is the inability to implement signature modes due to the high voltage reference coupled to the first transistor.
A second prior art protection device consists of a grounded gate n-channel transistor which may be coupled through a resistor to a pad. Although this method allows signature modes to be implemented, the device is not always effective in CMOS applications The studies have shown that the resistor fails or that n-channel devices fail during high energy events because of alloy spiking of the n+ junction In n-MOS processing, this defect can be overcome by utilizing deep n+ junctions. However, in CMOS processing shallow n+ junctions are often employed. As a result, the alloy spiking causes failure of n-channel protection devices. This defect can be overcome by enlarging the contact to gate spacing, but this requires additional silicon area which adds to the size of the integrated circuit.
Therefore, it is an object of the present invention to provide excess energy protection for semiconductor devices.
It is another the object of the present invention to provide excess energy protection which requires a minimum of silicon area.
It is a still further object of the present invention to provide excess energy protection without the use of deep n+ plugs.
It is yet another object of the present invention to provide excess energy protection which can be utilized with CMOS technology.